1. Field of the Invention
The present invention relates to a shift register having a plurality of register units connected in series. In particular, the invention relates to a shift register allowing high-speed data processing such as data insertion and other data processing, as well as to a control method of such a shift register.
2. Description of the Prior Art
Shift registers are used for processing of a data string in various electronic circuits. In communication devices, for example, processing of a data string is needed when it is desired to insert prescribed data or rearrange data so that they will be arranged in proper order, that is, in order of time or addresses.
Japanese Patent Application Laid-Open No. 56-131243 discloses a technique for that purpose in which a sync control signal composed of a plurality of bits is inserted into a digital signal data string by using a shift register and other circuit elements.
Conventionally, a data string processing function is realized by processing data in a software-like manner. For example, in the case of inserting data into a data string, a program is used, which shifts all data following a position where new data is to be inserted one by one and then inserts the new data at the resulting empty location.
Japanese Patent Application Laid-Open No. 6-350933 discloses a technique of starting a scanning from an arbitrary position in a shift register and stopping the scan at another arbitrary position, though the purpose of this technique is different from that of the present invention.
The above-described conventional data processing or constructing methods have a problem that considerable time is needed to insert even a single piece of data into an existing data string.
An object of the present invention is to provide a shift register capable of performing, with a relatively simple hardware-like configuration, such processing as data insertion much faster and more easily than in the conventional case of using software processing, as well as to a data inserting method using such a shift register and a control method of the shift register.
According to the present invention, a shift register includes: a plurality of register units connected in series, each of the register units having a direct input port which is selected for direct data input only when the register unit is designated; and a controller controlling the register units such that a desired register unit is designated to store direct data and all downstream register units starting from the designated register unit shift their data to respective ones of next stages.
According to an aspect of the present invention, a shift register includes: a plurality of register units connected in series, each of the register units comprises: an input selector for selecting one of first input data received from a previous stage and second input data received from a data bus, depending on a selection signal; and a storage element for storing and outputting the selected data to a next stage depending on a shift clock signal; and a controller controlling the selection signal and the shift clock signal such that only a designated register unit inputs the second input data from the data bus and only downstream register units starting from the designated register unit shift their data to respective ones of next stages.
According to another aspect of the present invention, a shift register includes: n (n greater than 1) register units connected in series, each of the register units comprises: m (m greater than 1) input selectors for selecting respective bits of first m-bit input data received from a previous stage and second m-bit input data received from a m-bit data bus, depending on a selection signal; and m storage elements for storing and outputting the selected m-bit data to a next stage depending on a shift clock signal; and a controller controlling the selection signal and the shift clock signal such that only a designated register unit inputs the second m-bit input data from the m-bit data bus and only downstream register units starting from the designated register unit shift their m-bit data to respective ones of next stages.
The controller may include: a shift position designator for generating the selection signal to a designated one of the register units depending on shift position designation data; and a shift clock generator for supplying the shift clock signal to each of the all downstream register units starting from the designated register unit.
According to the present invention, a data inserting method includes the steps of: a) storing an original string of data in a shift register having a plurality of register units connected in series, each of the register units having a direct input port for input of insertion data to be inserted; b) designating a desired one of the register units to cause the direct input port of the designated register unit to be active; c) shifting original data stored in all downstream register units starting from the designated register unit to respective ones of next stages; and d) inputting the insertion data in the designated register unit through the direct input port thereof, to produce a new string of data having the insertion data inserted therein.
The steps (c) and (d) may be performed in synchronization with each other.
According to further another aspect of the present invention, a control method of a shift register comprising a plurality of register units connected in series, each of the register units having a direct input port which is selected for direct data input only when the register unit is designated, includes the steps of: a) designating one of the register units depending on shift position designation data; and b) supplying a shift clock signal to each of all downstream register units starting from the designated register unit.
Each of the register units may include an input selector for selecting one of first input data received from a previous stage and second input data received from a data bus, depending on a selection signal; and a storage element for storing and outputting the selected data to a next stage depending on a shift clock signal. The step (a) may be the step of generating the selection signal to a designated one of the register units depending on shift position designation data. The step (b) may be the step of supplying the shift clock signal to each of the all downstream register units starting from the designated register unit.
Each of the register units may include; m (m greater than 1) input selectors for selecting respective bits of first m-bit input data received from a previous stage and second m-bit input data received from a m-bit data bus, depending on a selection signal; and m storage elements for storing and outputting the selected m-bit data to a next stage depending on a shift clock signal. The step (a) may be The step of generating the selection signal to a designated one of the register units depending on shift position designation data. The step (b) may be the step of supplying the shift clock signal to each of the all downstream register units starting from the designated register unit.
As described above, according to the present invention, in a state that a data string arranged in certain order is set in the shift register, desired data can be inputted to a desired register unit while sequentially shifting existing data to a subsequent register unit. Therefore, a manipulation such as inserting desired data into the data string at an arbitrary position can be performed simply at high speed on hardware.